CAN CARBON NANOTUBES BE COMPETITIVE
IN CHIP INTERCONNECT APPLICATIONS

Dusan Petranovic
Design to Silicon Division, Mentor Graphics Corp., 1001 Ridder Park Drive, San Jose, California, 95131, USA

Chip interconnects present one of the big challenges in gigascale integration. As the technology scales and interconnect wire width is getting down to 40 nm, copper resistance is increasing, due to atom scattering off the grain boundaries and rough edges, and   percentage increase of high resistivity cladding around the copper wires. Projection is that the resistivity will double as the copper wire widths get down to 20 nm. This will significantly slow down chip signal propagation and increase interconnect temperature.  Smaller wire cross sections will also create reliability problems due to increasing electro-migration. Carbon Nano-Tubes (CNTs) have recently been given a lot of research attention as possible replacement for copper wires in VLSI circuit interconnect. CNTs are graphene sheets rolled up as cylinders. They have high mechanical  stability, high thermal conductivity, extremely high current caring capacity, and  effectively no electro-migration, which all make them very attractive as a replacement for copper in chip interconnect application. There are, however, serious obstacles for the application. It is still a challenge to make the nanotubes with consistent properties and to arrange them in the desired patterns for chip interconnect applications, or to grow them where needed at the chip processing temperatures. In addition, high nanotube/metal contact resistance requires use of CNT bundles which poses additional challenges in CNT based interconnect implementation and characterization. This presentation will provide a comprehensive analysis of opportunities and challenges of CNT application in future VLSI circuit interconnect. A model developed for calculation of equivalent circuit parameters will be used to compare performance of CNT-based interconnects to copper-based one and to identify necessary technology requirements to make CNT-based interconnect viable in future application in various levels of chip interconnect. Special attention will be given to CNT applications as vias, in now prevailing 2D, as well as in emerging 3D chip manufacturing technologies.